Channel encoding

ABSTRACT

A channel encoding method of calculating, using a programmable processor, a code identical with a code obtained with a hardware channel encoder. The method comprises:—a first step ( 112, 120; 222 ) of reading the result of a first sub-system of parallel XOR operations between shifted bits in a first pre-computed lookup table at a memory address determined from the value of the inputted bits, the first pre-computed lookup table storing any possible result of the first sub-system at respective memory addresses, and—at least a step ( 116, 124; 226 ) of carrying out an XOR operation between the read result and the result of a second sub-system of parallel XOR operations using an XOR instruction of the programmable processor.

FIELD OF THE INVENTION

The present invention relates to channel encoding

BACKGROUND OF THE INVENTION

Hardware channel encoders may include the following elements to generatea code:

-   -   a shift register to shift an inputted set of bits by one bit,        and    -   XOR gates to carry out XOR operations between the shifted bits.

Some channel encoding methods which calculate a code identical with acode obtained with such a hardware channel encoder are implemented withprogrammable processors. These methods read the code in one pre-computedlookup table at a memory address determined from the inputted set ofbits.

The size of the lookup table is proportional to 2^(n+k), where n is thenumber of inputted bits processed in parallel and k is an integer alsoknown as the constraint length.

For example, WO 03/52997 (in the name of HURT James Y et al.) disclosessuch a method.

The size of the lookup table is important and therefore the methodrequires a large memory space, which is not always available on portableuser equipment such as mobile phones.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide a channelencoding method designed to be implemented with a programmableprocessor, which requires less memory space.

The invention provides a channel encoding method designed to beimplemented with a programmable processor capable of executing XORoperations in response to XOR instructions, wherein the methodcomprises:

-   -   a first step of reading the result of a first sub-system of        parallel XOR operations between shifted bits in a first        pre-computed lookup table at a memory address determined from        the value of the inputted bits, the first pre-computed lookup        table storing any possible result of the first sub-system at        respective memory addresses, and    -   at least a step of carrying out an XOR operation between the        read result and the result of a second sub-system of parallel        XOR operations using the XOR instruction of the programmable        processor.

The above method mixes computation of XOR operations by using a lookuptable and by using XOR instructions. Therefore, on the one hand, thesize of the lookup table is smaller than with a conventional channelencoding method using no XOR instructions. On the other hand, the numberof XOR instructions used to compute the code is smaller than with achannel encoding method using no lookup table. As a result, this methodis well-suited to implement on portable user equipment having littlememory space or on base stations.

The features of claim 2 reduce the number of operations to be performedby the processor.

The features of claim 3 reduce the memory space necessary to implement aconvolutional encoding method on a programmable processor.

The features of claim 4 reduce the memory space necessary to implement achannel encoding method corresponding to a hardware channel encoderhaving at least a feedback chain, e.g., a turbo encoder.

The features of claim 5 reduce the memory space necessary to implementthe channel encoding method on a programmable processor.

The features of claim 6 reduce the number of operations to be performedby the processor because it is not necessary to carry out multiplexingoperations.

The invention also relates to a memory and a processor program toexecute the above channel encoding method as well as to a channelencoder, user equipment and a base station implementing the method.

These and other aspects of the invention will be apparent from thefollowing description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a hardware turbo encoder;

FIG. 2 is a schematic diagram of a forward chain of the turbo encoder ofFIG. 1;

FIG. 3 is a schematic diagram of a feedback chain of the turbo encoderof FIG. 1;

FIG. 4 is a schematic diagram of user equipment having a programmableprocessor which executes a channel encoding method;

FIG. 5 is a flowchart of a channel encoding method implemented in theuser equipment of FIG. 4;

FIG. 6 is a schematic diagram of a hardware convolutional encoder;

FIG. 7 is a schematic diagram of user equipment having a programmableprocessor to execute a convolutional encoding method; and

FIG. 8 is a flowchart of a convolutional encoding method implemented inthe user equipment of FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a hardware turbo encoder 2. For simplicity, only thedetails necessary to understand the invention are shown in FIG. 1.

More details on the element of encoder 2 may be found in 3G wirelessstandards such as 3GPP (3^(rd) Generation Partnership Project) UTRATDD/FDD and 3GPP2 CDMA2000.

Like any channel encoder, turbo encoder 2 is designed to add redundancyin an inputted bit stream. For example, encoder 2 outputs three bitsX[i], Z[i] and Z′[i] for each bit d_(i) of the inputted bit stream.Index i represents the instant at which bit d_(i) is inputted in encoder2. Index i is equal to zero when the first bit d₀ is inputted and isincremented by one each time a new bit is inputted. Typically, theinstant at which a bit d _(i) is inputted in encoder 2 corresponds tothe raising edge of a clock signal.

Encoder 2 has two identical left feedback shift registers 4 and 6 andone interleaver 10.

Shift register 4 includes four memory elements 14 to 17 connected inseries. Memory element 14 is connected to an input 22 to receive newbits d_(i) and memory element 17 is connected to an output 24. Output 24is connected to the first inputs of two XOR gates 26 and 28. The secondinput of XOR gate 26 is connected to an output of a XOR gate 30.

The second input of XOR gate 28 is connected at an output of memoryelement 16.

An output of XOR gate 26 is connected to a terminal 32 to output bitZ[i].

An output of XOR gate 28 is connected to a first input of XOR gate 34. Asecond input of XOR gate 34 is connected to an output of memory element14 through a two-position switch 36.

An output of XOR gate 34 is connected to an input of memory element 15and to a second input of XOR gate 30.

In a first position, switch 36 connects the output of memory element 14to the second input of XOR gate 34.

In a second position, switch 36 connects the output of XOR gate 28 tothe second input of XOR gate 34.

Switch 36 is shifted to the second position only to encode the end of aninputted bit stream. This connection is represented in a dashed line.

The second input of XOR gate 34 is also connected to a terminal 40 tooutput bit X[i].

Each memory element is intended to store one bit and to shift this bitto the next memory element at each instant i.

The value of bits r₄[i], r₃[i], r₂[i] and r₁[i] of a remainder r arestored in shift register 4.

The values of bits r₄[i], r₃[i], r₂[i] and r₁[i] are equal to the valueof signals at the inputs of memory elements 15, 16 and 17 and at theoutput of memory element 17, respectively. The remainder value is afunction of the values of the inputted bits d_(i) and of the previousbits r₄[I−1], r₃[I−1], r₂[I−1] and r₁ [I−1].

Shift register 6 also includes four memory elements 50-53 connected inseries.

The connection of memory elements 50-53 to each other is identical withthe connection of memory elements 14-17 and will not be described indetail. The connections between memory elements 50-53 also use four XORgates 56, 58, 60 and 64 and one switch 66 corresponding to XOR gates 26,28, 30 and 34 and switch 36, respectively.

Shift register 6 is connected to two terminals 70 and 72. Terminal 70 isconnected to the output of XOR gate 56 to output bit Z′[i]. Terminal 72is connected to the output of XOR gate 58 to output a bit X′[i] at theend of the encoding of the bit stream. This connection is represented ina dashed line.

The set of bits r′₄[i], r′₃[i], r′₂[i] and r′₁[i] of a remainder r′ isstored in shift register 6.

The values of bits r′₄[i], r′₃[i], r′₂[i] and r′₁[i] are equal to thevalues of the signals at the inputs of memory elements 51, 52 and 53 andat the output of memory element 53. The value of remainder r′ is afunction of the values of inputted bits e_(i) and of the previous valueof bits r′₄[I−1], r′₃[I−1], r′₂[I−1] and r′₁[I−1].

Memory element 50 has an input 65 to receive bits e_(i).

Interleaver 10 has an input connected to input 22 and an outputconnected to input 65. Interleaver 10 mixes bits d_(i) from the inputtedbit stream and outputs a mixed bit stream made of bits e_(i).

FIGS. 2 and 3 show details of encoder 2. In FIGS. 2 and 3, the elementsalready described in FIG. 1 have the same references.

FIG. 2 shows a forward chain of encoder 2. The forward chain includesXOR gates 26 and 30. Output bits Z[i] of the forward chain at instant ican be computed with the following relation:

Z[i]=r₄[i]⊕r₃[i]⊕r₁[i]  (1)

where the symbol ⊕ is an XOR operation.

FIG. 3 shows in more detail a feedback chain of encoder 2. The feedbackchain shown includes XOR gates 28 and 34. This feedback chaincorresponds to the following relation:

r₄[i]=d_(i−1)⊕r₂[i]⊕r₁[i]  (2)

The following relations can also be derived from the schematic diagramof encoder 2:

r ₃ [i]=r ₄ [i−1]

r ₂ [i]=r ₃ [i−1]

r ₁ [i]=r ₂ [i−1]  (3)

The following system Z of parallel XOR operations is derived fromrelation (1) to calculate in parallel five successive output bits Z[i]to Z[i+4]:

$\begin{matrix}{Z = \left\{ \begin{matrix}{{Z\lbrack i\rbrack} = {{r_{4}\lbrack i\rbrack} \oplus {r_{3}\lbrack i\rbrack} \oplus {r_{1}\lbrack i\rbrack}}} \\{{Z\left\lbrack {i + 1} \right\rbrack} = {{r_{4}\left\lbrack {i + 1} \right\rbrack} \oplus {r_{3}\left\lbrack {i + 1} \right\rbrack} \oplus {r_{1}\left\lbrack {i + 1} \right\rbrack}}} \\{{Z\left\lbrack {i + 2} \right\rbrack} = {{r_{4}\left\lbrack {i + 2} \right\rbrack} \oplus {r_{3}\left\lbrack {i + 2} \right\rbrack} \oplus {r_{1}\left\lbrack {i + 2} \right\rbrack}}} \\{{Z\left\lbrack {i + 3} \right\rbrack} = {{r_{4}\left\lbrack {i + 3} \right\rbrack} \oplus {r_{3}\left\lbrack {i + 3} \right\rbrack} \oplus {r_{1}\left\lbrack {i + 3} \right\rbrack}}} \\{{Z\left\lbrack {i + 4} \right\rbrack} = {{r_{4}\left\lbrack {i + 4} \right\rbrack} \oplus {r_{3}\left\lbrack {i + 4} \right\rbrack} \oplus {r_{1}\left\lbrack {i + 4} \right\rbrack}}}\end{matrix} \right.} & (4)\end{matrix}$

Using relations (2) and (3), it is possible to write system Z using onlythe bits of the remainder r at instant i:

$\begin{matrix}{Z = \left\{ \begin{matrix}{{Z\lbrack i\rbrack} = {d_{i - 1} \oplus {r_{2}\lbrack i\rbrack} \oplus {r_{3}\lbrack i\rbrack}}} \\{{Z\left\lbrack {i + 1} \right\rbrack} = {d_{i} \oplus d_{i - 1} \oplus {r_{3}\lbrack i\rbrack} \oplus {r_{2}\lbrack i\rbrack} \oplus {r_{1}\lbrack i\rbrack}}} \\{{Z\left\lbrack {i + 2} \right\rbrack} = {d_{i + 1} \oplus d_{i} \oplus d_{i - 1} \oplus {r_{1}\lbrack i\rbrack} \oplus {r_{3}\lbrack i\rbrack}}} \\{{Z\left\lbrack {i + 3} \right\rbrack} = {d_{i + 2} \oplus d_{i + 1} \oplus d_{i} \oplus d_{i - 1} \oplus {r_{1}\lbrack i\rbrack}}} \\{{Z\left\lbrack {i + 4} \right\rbrack} = {d_{i + 3} \oplus d_{i + 2} \oplus d_{i + 1} \oplus d_{i} \oplus {r_{2}\lbrack i\rbrack}}}\end{matrix} \right.} & (5)\end{matrix}$

Thus, according to relation (5) bits Z[i] to Z[i+4] can be computed fromthe set of bits [d_(i−1), . . . , d_(i+3)] and from the value of bitsr₁[i], r₂[i] and r₃[i] at instant i.

A system r[i+5] to calculate in parallel the value of bits r₁[I+5],r₂[I+5] and r₃[I+5] at instant i+5 from the values of bits r₁[i], r₂[i]and r₃[i] at instant i can be derived from relations (2) and (3). Systemr[i+5] is as follows:

$\begin{matrix}{{r\left( {i + 5} \right)} = \left\{ \begin{matrix}{{r_{3}\left\lbrack {i + 5} \right\rbrack} = {d_{i + 3} \oplus d_{i + 1} \oplus d_{i} \oplus d_{i - 1} \oplus {r_{1}\lbrack i\rbrack}}} \\{{r_{2}\left\lbrack {i + 5} \right\rbrack} = {d_{i + 2} \oplus d_{i} \oplus d_{i - 1} \oplus {r_{3}\lbrack i\rbrack} \oplus {r_{1}\lbrack i\rbrack}}} \\{{r_{1}\left\lbrack {i + 5} \right\rbrack} = {d_{i + 1} \oplus d_{i - 1} \oplus {r_{3}\lbrack i\rbrack} \oplus {r_{2}\lbrack i\rbrack} \oplus {r_{1}\lbrack i\rbrack}}}\end{matrix} \right.} & (6)\end{matrix}$

From the schematic diagram of FIG. 1, a system X to compute in parallelbits X[i] to X[i+4] can be written as follows:

$\begin{matrix}{X = \left\{ \begin{matrix}{{X\lbrack i\rbrack} = d_{i - 1}} \\{{X\left\lbrack {i + 1} \right\rbrack} = d_{i}} \\{{X\left\lbrack {i + 2} \right\rbrack} = d_{i + 1}} \\{{X\left\lbrack {i + 3} \right\rbrack} = d_{i + 2}} \\{{X\left\lbrack {i + 4} \right\rbrack} = d_{i + 3}}\end{matrix} \right.} & (7)\end{matrix}$

In a similar way, a system Z′ of parallel XOR operations to calculate inparallel bits Z′[i] to Z′[i+4] from the value of a set of bits {e_(i−1);. . . ; e_(i+3)} and the values of bits r′₁[i], r′₂[i], and r′₃[i] canbe derived from FIG. 1. System Z is as follows:

$\begin{matrix}{Z^{\prime} = \left\{ \begin{matrix}{{Z^{\prime}\lbrack i\rbrack} = {e_{i - 1} \oplus {r_{2}^{\prime}\lbrack i\rbrack} \oplus {r_{3}^{\prime}\lbrack i\rbrack}}} \\{{Z^{\prime}\left\lbrack {i + 1} \right\rbrack} = {e_{i} \oplus e_{i - 1} \oplus {r_{3}^{\prime}\lbrack i\rbrack} \oplus {r_{2}^{\prime}\lbrack i\rbrack} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}} \\{{Z^{\prime}\left\lbrack {i + 2} \right\rbrack} = {e_{i + 1} \oplus e_{i} \oplus e_{i - 1} \oplus {r_{1}^{\prime}\lbrack i\rbrack} \oplus {r_{3}^{\prime}\lbrack i\rbrack}}} \\{{Z^{\prime}\left\lbrack {i + 3} \right\rbrack} = {e_{i + 2} \oplus e_{i + 1} \oplus e_{i} \oplus e_{i - 1} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}} \\{{Z^{\prime}\left\lbrack {i + 4} \right\rbrack} = {e_{i + 3} \oplus e_{i + 2} \oplus e_{i + 1} \oplus e_{i} \oplus {r_{2}^{\prime}\lbrack i\rbrack}}}\end{matrix} \right.} & (8)\end{matrix}$

Similarly, system r′ [i+5] of parallel XOR operations to calculate inparallel bits r′₁[i+5], r′₂[i+5] and r′₃[i+5] is derived from FIG. 1.System r′[i+5] is as follows:

$\begin{matrix}{{r^{\prime}\left( {i + 5} \right)} = \left\{ \begin{matrix}{{r_{3}^{\prime}\left\lbrack {i + 5} \right\rbrack} = {e_{i + 3} \oplus e_{i + 1} \oplus e_{i} \oplus e_{i - 1} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}} \\{{r_{2}^{\prime}\left\lbrack {i + 5} \right\rbrack} = {e_{i + 2} \oplus e_{i} \oplus e_{i - 1} \oplus {r_{3}^{\prime}\lbrack i\rbrack} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}} \\{{r_{1}^{\prime}\left\lbrack {i + 5} \right\rbrack} = {e_{i + 1} \oplus e_{i - 1} \oplus {r_{3}^{\prime}\lbrack i\rbrack} \oplus {r_{2}^{\prime}\lbrack i\rbrack} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}}\end{matrix} \right.} & (9)\end{matrix}$

System Z can be pre-computed for any possible value of the set of bits{d_(i−1); . . . ; d_(i+3)} and bit values r₁[i], r₂[i], r₃[i] and theresults stored in a lookup table Z. Thus, lookup table Z contains 2⁸×5bits. In a similar way, the results of system r[i+5], system Z′, andsystem r′[i+5] can be pre-computed for any possible set of inputted bitsand any possible remainder value. As a result, implementing a turboencoding method using lookup tables for systems Z, r[i+5], Z′ andr′[i+5] requires a memory storing 2⁸×5+2⁸×3+2⁸×5+2⁸×3 bits.

The result of system X can be read directly from the received bit d_(i).

This memory space can be too large to store these lookup tables in userequipment such as a mobile phone. The following part of the descriptionexplains how it is possible to reduce the size of the lookup tables.

System Z can be split up into two sub-systems ZP and R_(e) because XORoperations are interchangeable:

Z=ZP⊕R_(e)  (10)

where

$\begin{matrix}{{ZP} = \left\{ \begin{matrix}{{{ZP}\lbrack i\rbrack} = d_{i - 1}} \\{{{ZP}\left\lbrack {i + 1} \right\rbrack} = {d_{i} \oplus d_{i - 1}}} \\{{{ZP}\left\lbrack {i + 2} \right\rbrack} = {d_{i + 1} \oplus d_{i} \oplus d_{i - 1}}} \\{{{ZP}\left\lbrack {i + 3} \right\rbrack} = {d_{i + 2} \oplus d_{i + 1} \oplus d_{i} \oplus d_{i - 1}}} \\{{{ZP}\left\lbrack {i + 4} \right\rbrack} = {d_{i + 3} \oplus d_{i + 2} \oplus d_{i + 1} \oplus d_{i}}}\end{matrix} \right.} & (11) \\{R_{e} = \left\{ \begin{matrix}{{R_{e}\lbrack i\rbrack} = {\oplus {{r_{2}\lbrack i\rbrack} \oplus {r_{3}\lbrack i\rbrack}}}} \\{{R_{e}\left\lbrack {i + 1} \right\rbrack} = {\oplus {{r_{3}\lbrack i\rbrack} \oplus {r_{2}\lbrack i\rbrack} \oplus {r_{1}\lbrack i\rbrack}}}} \\{{R_{e}\left\lbrack {i + 2} \right\rbrack} = {\oplus {{r_{1}\lbrack i\rbrack} \oplus {r_{3}\lbrack i\rbrack}}}} \\{{R_{e}\left\lbrack {i + 3} \right\rbrack} = {\oplus {r_{1}\lbrack i\rbrack}}} \\{{R_{e}\left\lbrack {i + 4} \right\rbrack} = {r_{2}\lbrack i\rbrack}}\end{matrix} \right.} & (12)\end{matrix}$

The value of sub-system ZP can be computed beforehand using only thevalue of the set of bits {d_(i−1); . . . ; d_(i+3)} and sub-system R_(e)can be computed using only the value of remainder r[i]. Thus, a lookuptable ZP comprising all the results of sub-system ZP for any possiblevalue of the set of bits {d_(i−1); . . . ; d_(i+3)} comprises only 2⁵−5bits. Each result of sub-system ZP is stored at a respective memoryaddress determined from the value of the set of bits {d_(i−1); . . . ;d_(i+3)}.

A lookup table R_(e) comprising the results of sub-system R_(e) for anypossible value of remainder r[i] stores only 2³−5 bits. In table R_(e),each result of sub-system R_(e) is stored at a respective memory addressdetermined from the value of bits r₁[i], r₂[i], r₃[i].

Therefore, using two lookup tables ZP and R_(e) instead of lookup tableZ reduces the memory space necessary to implement the turbo encodingmethod.

In a similar way, the result of system Z′ can be computed from theresult of two sub-systems ZP′ and R_(e)′ using the following relation:

Z′=ZP′⊕R_(e)′  (13)

where:

$\begin{matrix}{{ZP}^{\prime} = \left\{ \begin{matrix}{{{ZP}^{\prime}\lbrack i\rbrack} = e_{i - 1}} \\{{{ZP}^{\prime}\left\lbrack {i + 1} \right\rbrack} = {e_{i} \oplus e_{i - 1}}} \\{{{ZP}^{\prime}\left\lbrack {i + 2} \right\rbrack} = {e_{i + 1} \oplus e_{i - 1}}} \\{{{ZP}^{\prime}\left\lbrack {i + 3} \right\rbrack} = {e_{i + 2} \oplus e_{i + 1} \oplus e_{i} \oplus e_{i - 1}}} \\{{{ZP}^{\prime}\left\lbrack {i + 4} \right\rbrack} = {e_{i + 3} \oplus e_{i + 2} \oplus e_{i + 1} \oplus e_{i}}}\end{matrix} \right.} & (14) \\{R_{e}^{\prime} = \left\{ \begin{matrix}{{R_{e}^{\prime}\lbrack i\rbrack} = {\oplus {{r_{2}^{\prime}\lbrack i\rbrack} \oplus {r_{3}^{\prime}\lbrack i\rbrack}}}} \\{{R_{e}^{\prime}\left\lbrack {i + 1} \right\rbrack} = {{r_{3}^{\prime}\lbrack i\rbrack} \oplus {r_{2}^{\prime}\lbrack i\rbrack} \oplus {r_{1}^{\prime}\lbrack i\rbrack}}} \\{{R_{e}^{\prime}\left\lbrack {i + 2} \right\rbrack} = {{r_{1}^{\prime}\lbrack i\rbrack} \oplus {r_{3}^{\prime}\lbrack i\rbrack}}} \\{{R_{e}^{\prime}\left\lbrack {i + 3} \right\rbrack} = {r_{1}^{\prime}\lbrack i\rbrack}} \\{{R_{e}^{\prime}\left\lbrack {i + 4} \right\rbrack} = {r_{2}^{\prime}\lbrack i\rbrack}}\end{matrix} \right.} & (15)\end{matrix}$

The pre-computed results of system ZP′ for each value of the set of bits{e_(i−1); . . . ; e_(i+3)} are stored in a lookup table ZP′ and theresults of sub-system R_(e)′ for any possible value of remainder r′[i]are stored in a lookup table R_(e)′.

The values of bits X[i] to X[i+4] are read from the values of the set ofbits {d_(i−1); . . . ; d_(i+3)}.

FIG. 4 shows user equipment 90 including channel encoder 91 having aprogrammable microprocessor 92 and a memory 94.

User equipment 90 is, for example, a mobile phone.

Microprocessor 92 has an input 96 to receive the stream of bits d_(i)and an output 98 to output a turbo encoded bit stream.

Memory 94 stores lookup table ZP, R_(e), r[i+5], ZP′ and Re′. Lookuptable r′[i+5] is identical with lookup table r[i+5] and only this lastlookup table is stored in memory 94.

Microprocessor 92 is adapted to execute a microprocessor program 100stored, for example, in memory 94. Program 100 includes instructions forthe execution of the turbo encoding method of FIG. 5. Processor 92 isadapted to execute an XOR operation in response to an XOR instructionstored in memory 94.

The operation of processor 92 will now be described with reference toFIG. 5.

Initially, all the remainders r and r′ are null.

In step 110, processor 92 receives the first set of bits {d₀; . . . ;d₄}. Then, in step 112, processor 92 reads in parallel the bit valuesX[1] to X[5] and ZP[1] to ZP[5] in lookup table ZP at the memory addressdetermined from the value of the set of bits {d₀; . . . ; d₄}.

In step 114, processor 92 also reads in parallel bits R_(e)[1] toR_(e)[5] in lookup table R_(e) at the memory address determined from thevalues of bits r₃[1], r₂[1] and r₁[1] which are all null.

Subsequently, in step 116, processor 92 carries out an XOR operationbetween the result of sub-system ZP read in step 112 and the result ofsub-system R_(e) read in step 114 to obtain the value of bits Z[1] toZ[5] according to relation (10).

Parallel to steps 112-116, in step 118, processor 92 interleaves thereceived bits to generate the interleaved bit stream e_(i).

Thereafter, in step 120, the values of bits ZP′[1] to ZP′[5] are read inparallel in lookup table ZP′ at the memory address determined from thevalue of the set of bits {e₀; . . . ; c₄}.

In step 122, processor 92 reads in parallel the values of bits R_(e)′[1]to R_(e)′[4] in lookup table Re′ using the values of bits r′₃[1], r′₂[1]and r′₁[1], which are all null. Then, in step 124, processor 92 carriesout an XOR operation between the results read in steps 120 and 122 toobtain the values of bits Z′[1] to Z′[5] according to relation (13).

Once the values of bits X[1] to X[5]; Z[1] to Z[5] and Z′[1] to Z′[5]are known, in step 130, processor 92 combines these bit values togenerate the turbo encoded bit stream outputted through output 98. Theturbo encoded bit stream includes the bit values in the following orderX[i], Z[i], Z′[i], X[i+1], Z[i+1], Z′[i+1], . . . and so on.

Thereafter, in step 132, processor 92 reads the values of remainder rand r′ necessary for the next iteration of steps 114 and 122 in lookuptable r[i+5]. More precisely, during operation 134, processor 92 readsin parallel the values of bits r₁[6], r₂[6] and r₃[6] in lookup tabler[i+5] at the memory address determined from the value of bits r₃[1],r₂[1] and r₁[1] and bits d₀ to d₄. In operation 136, microprocessor 92reads in parallel the next values of bits r′₁[6], r′₂[6], r′₁[6]necessary for the next iteration of step 122 in lookup table r[i+5] atthe memory address determined from the values of bits r′₃[1], r′₂[1] andr′₁[1].

Then, microprocessor 92 returns to step 110 to receive the next fivebits d_(i) of the inputted bit stream.

Steps 112 to 132 are then repeated using the received new set of bitsand the calculated new value for remainder r and r′.

The method of FIG. 5 when implemented in a programmable microprocessorlike microprocessor 92, allows to compute a turbo encoded bitstreamidentical with the one generated by the hardware turbo encoder 2.

FIG. 6 shows a hardware convolutional encoder 150 which is anotherexample of a hardware channel encoder. More precisely, encoder 150 is aconvolutional encoder having a rate of 1/2. A rate of 1/2 means that foreach bit d_(i) of the inputted bit stream, encoder 150 generates twobits of the encoded bit stream.

FIG. 6 shows only the details necessary to understand the invention.More details on such a convolutional encoder may be found in 3G wirelessstandards such as 3GPP UTRA TDD/FDD and 3GPP2 CDMA2000 previously cited.

Encoder 150 includes a shift register 152 having nine memory elements154 to 162 connected in series. Element 154 has an input 166 to receivebits d_(i) of the input bit stream to be encoded.

Encoder 150 has two forward chains. The first forward chain is builtusing XOR gates 170, 172, 174 and 176 and outputs a bit D1[i] at instanti.

XOR gate 170 has one input connected to an output of memory element 154and a second input connected to the output of memory element 156. XORgate 170 has also an output connected to the first input of XOR gate172. A second input of XOR gate 172 is connected to an output of memoryelement 156. An output of XOR gate 172 is connected to a first input ofXOR gate 174. A second input of XOR gate 174 is connected to an outputof memory element 158. An output of XOR gate 174 is connected to a firstinput of XOR gate 176. A second input of XOR gate 176 is connected to anoutput of memory element 162. An output of XOR gate 176 outputs bitD1[i] and is connected to a first input of a multiplexer 180.

The second forward chain is built using XOR gates 182, 184, 186, 188,190 and 192.

XOR gate 182 has two inputs connected to the output of memory elements154 and 155, respectively.

XOR gate 184 has two inputs connected to an output of XOR gate 182 andthe output of memory element 156, respectively.

XOR gate 186 has two inputs connected to an output of XOR gate 184 andthe output of memory element 157, respectively.

XOR gate 188 has two inputs connected to an output of XOR gate 186 andan output of memory element 159, respectively.

XOR gate 190 has two inputs connected to an output of XOR gate 188 andto an output of memory element 161, respectively.

XOR gate 192 has two inputs connected to an output of XOR gate 190 andto the output of memory element 162, respectively. XOR gate 192 has alsoan output to generate a bit D2[i], which is connected to a second inputof multiplexer 180.

Multiplexer 180 converts bit D1[i] and D2[i] received in parallel on itsinputs into a serial bit stream alternating the bit D1[i] and D2[i]generated by the two forward chains.

Sixteen consecutive output bits of the encoded output bit stream can becomputed in parallel using a system D as follows:

$\begin{matrix}{D = \left\{ \begin{matrix}{{D\; {1\lbrack i\rbrack}} = {d_{i + 8} \oplus d_{i + 6} \oplus d_{i + 5} \oplus d_{+ 4} \oplus d_{i}}} \\{{D\; {2\lbrack i\rbrack}} = {d_{i + 8} \oplus d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 5} \oplus d_{i + 3} \oplus d_{i + 1} \oplus d_{i}}} \\{{D\; {1\left\lbrack {i + 1} \right\rbrack}} = {d_{i + 9} \oplus d_{i + 7} \oplus d_{i + 6} \oplus d_{+ 5} \oplus d_{i + 1}}} \\{{D\; {2\left\lbrack {i + 1} \right\rbrack}} = {d_{i + 9} \oplus d_{i + 8} \oplus d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 4} \oplus d_{i + 2} \oplus d_{i + 1}}} \\{{D\; {1\left\lbrack {i + 2} \right\rbrack}} = {d_{i + 10} \oplus d_{i + 8} \oplus d_{i + 7} \oplus d_{+ 6} \oplus d_{i + 2}}} \\{{D\; {2\left\lbrack {i + 2} \right\rbrack}} = {d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 8} \oplus d_{i + 7} \oplus d_{i + 5} \oplus d_{i + 3} \oplus d_{i + 2}}} \\{{D\; {1\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 11} \oplus d_{i + 9} \oplus d_{i + 8} \oplus d_{+ 7} \oplus d_{i + 3}}} \\{{D\; {2\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 8} \oplus d_{i + 6} \oplus d_{i + 4} \oplus d_{i + 3}}} \\{{D\; {1\left\lbrack {i + 4} \right\rbrack}} = {d_{i + 12} \oplus d_{i + 10} \oplus d_{i + 9} \oplus d_{+ 8} \oplus d_{i + 4}}} \\{{D\; {2\left\lbrack {i + 4} \right\rbrack}} = {d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 7} \oplus d_{i + 5} \oplus d_{i + 4}}} \\{{D\; {1\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 13} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{+ 9} \oplus d_{i + 5}}} \\{{D\; {2\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 8} \oplus d_{i + 6} \oplus d_{i + 5}}} \\{{D\; {1\left\lbrack {i + 6} \right\rbrack}} = {d_{i + 14} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{+ 10} \oplus d_{i + 6}}} \\{{D\; {2\left\lbrack {i + 6} \right\rbrack}} = {d_{i + 14} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 9} \oplus d_{i + 7} \oplus d_{i + 6}}} \\{{D\; {1\left\lbrack {i + 7} \right\rbrack}} = {d_{i + 15} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{+ 11} \oplus d_{i + 7}}} \\{{D\; {2\left\lbrack {i + 7} \right\rbrack}} = {d_{i + 15} \oplus d_{i + 14} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 10} \oplus d_{i + 8} \oplus d_{i + 7}}}\end{matrix} \right.} & (16)\end{matrix}$

System D shows that a block of 16 consecutive bits of the encoded outputbit stream can be computed from the value of the set of bits {d_(i); . .. ; d_(i+15)}. Note that system D carries out the multiplexing operationof multiplexer 180. It is also possible to pre-compute the results ofsystem D for any possible value of the set of bits {d_(i); . . . ;d_(i−15)} and to record each result in a lookup table D at a memoryaddress determined from the value of the set of input bits {d_(i); . . .; d_(i+15)}. Lookup table D contains 2¹⁶×16 bits. The memory space usedto implement a convolutional encoding method using system D can bereduced by splitting up system D into two sub-systems DP1 and DP2 asfollows:

D=DP1⊕DP2  (17)

where:

$\begin{matrix}{{{DP}\; 1} = \left\{ \begin{matrix}{{{DP}\; {1\lbrack i\rbrack}} = {d_{i + 6} \oplus d_{i + 5} \oplus r_{i + 4} \oplus d_{i}}} \\{{{DP}\; {1\left\lbrack {i + 1} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 5} \oplus d_{i + 3} \oplus d_{i + 1} \oplus d_{i}}} \\{{{DP}\; {1\left\lbrack {i + 2} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 5} \oplus d_{i + 1}}} \\{{{DP}\; {1\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 4} \oplus d_{i + 2} \oplus d_{i + 1}}} \\{{{DP}\; {1\left\lbrack {i + 4} \right\rbrack}} = {\oplus {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 2}}}} \\{{{DP}\; {1\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 5} \oplus d_{i + 3} \oplus d_{i + 2}}} \\{{{DP}\; {1\left\lbrack {i + 6} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 3}}} \\{{{DP}\; {1\left\lbrack {i + 7} \right\rbrack}} = {d_{i + 6} \oplus d_{i + 4} \oplus d_{i + 3}}} \\{{{DP}\; {1\left\lbrack {i + 8} \right\rbrack}} = d_{i + 4}} \\{{{DP}\; {1\left\lbrack {i + 9} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 5} \oplus d_{i + 4}}} \\{{{DP}\; {1\left\lbrack {i + 10} \right\rbrack}} = d_{i + 5}} \\{{{DP}\; {1\left\lbrack {i + 11} \right\rbrack}} = {d_{i + 6} \oplus d_{i + 5}}} \\{{{DP}\; {1\left\lbrack {i + 12} \right\rbrack}} = d_{i + 6}} \\{{{DP}\; {1\left\lbrack {i + 13} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6}}} \\{{{DP}\; {1\left\lbrack {i + 14} \right\rbrack}} = d_{i + 7}} \\{{{DP}\; {1\left\lbrack {i + 15} \right\rbrack}} = d_{i + 7}}\end{matrix} \right.} & (18) \\{{{DP}\; 2} = \left\{ \begin{matrix}{{{DP}\; {2\lbrack i\rbrack}} = d_{i + 8}} \\{{{DP}\; {2\left\lbrack {i + 1} \right\rbrack}} = d_{i + 8}} \\{{{DP}\; {2\left\lbrack {i + 2} \right\rbrack}} = d_{i + 9}} \\{{{DP}\; {2\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 9} \oplus d_{i + 8}}} \\{{{DP}\; {2\left\lbrack {i + 4} \right\rbrack}} = {d_{i + 10} \oplus d_{i + 8}}} \\{{{DP}\; {2\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 8}}} \\{{{DP}\; {2\left\lbrack {i + 6} \right\rbrack}} = {d_{i + 11} \oplus d_{i + 9} \oplus d_{i + 8}}} \\{{{DP}\; {2\left\lbrack {i + 7} \right\rbrack}} = {d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 8}}} \\{\; {{{DP}\; {2\left\lbrack {i + 8} \right\rbrack}} = {d_{i + 12} \oplus d_{i + 10} \oplus d_{i + 9} \oplus d_{i + 8}}}} \\{\; {{{DP}\; {2\left\lbrack {i + 9} \right\rbrack}} = {d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 9}}}} \\{{{DP}\; {2\left\lbrack {i + 10} \right\rbrack}} = {d_{i + 13} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 9}}} \\{{{DP}\; {2\left\lbrack {i + 11} \right\rbrack}} = {d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 10} \oplus d_{i + 8}}} \\{{{DP}\; {2\left\lbrack {i + 12} \right\rbrack}} = {d_{i + 14} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 10}}} \\{{{DP}\; {2\left\lbrack {i + 13} \right\rbrack}} = {d_{i + 14} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 11} \oplus d_{i + 9}}} \\{{{DP}\; {2\left\lbrack {i + 14} \right\rbrack}} = {d_{i + 15} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 11}}} \\{\; {{{DP}\; {2\left\lbrack {i + 15} \right\rbrack}} = {d_{i + 15} \oplus d_{i + 14} \oplus d_{i + 13} \oplus d_{i + 12} \oplus d_{i + 10} \oplus d_{i + 8}}}}\end{matrix} \right.} & (19)\end{matrix}$

The results of sub-system DP1 can be pre-computed for each value of theset of bits {d_(i); . . . ; d_(i+7)}. Each result of the pre-computationof sub-system DP1 is stored in a lookup table DP1 at an addressdetermined from the corresponding value of the set of bits {d_(i); . . .; d₇}. Lookup table DP1 only includes 2⁸×16 bits.

Similarly, each result of sub-system DP2 can be stored in a lookup tableDP2 at a memory address determined from the corresponding value of theset of bits {d_(i+8); . . . ; d_(i+15)}.

Therefore, implementing the convolutional encoding method using lookuptables DP1 and DP2 instead of lookup table D, decreases the memory spacenecessary for this implementation.

FIG. 7 shows user equipment 200 including a convolutional encoder 201having a programmable microprocessor 202 connected to a memory 204.

For example, user equipment 200 is a mobile phone.

Microprocessor 202 has an input 206 to receive the bit stream to beencoded and an output 208 to output the encoded bit stream.

Processor 202 executes instructions stored in a memory, for example, inmemory 204. Processor 202 is also adapted to execute an XOR operation inresponse to an XOR instruction.

Memory 204 stores a microprocessor program 210 having instructions forthe execution of the method of FIG. 8 when executed by processor 202.Memory 204 also stores lookup tables DP1 and DP2.

The operation of microprocessor 202 will now be described with referenceto FIG. 8.

Initially, in step 220, microprocessor 202 receives a new set of bits{d_(i); . . . ; d_(i+15)}. Then, in step 222, microprocessor 202 readsin parallel in lookup table DP1 the values of bits DP1[i] to DP1[i+15]at a memory address only determined by the value of the set of bits{d_(i); . . . ; d_(i+7)}.

Subsequently, in step 224, microprocessor 202 reads in parallel inlookup table DP2 the values of bits DP2[i] to DP2[i+15] at a memoryaddress only determined by the value of the set of bits {d_(i+8); . . .; d_(i+15)}.

Thereafter, in step 226, microprocessor 202 carries out an XOR operationbetween the results of a sub-system DP1 and DP2 to calculate bits D1[i]to D1[i+7] and D2[i] to D2[i+7] according to relation (17).

In step 228, the encoded bits are outputted through output 208.

Then, steps 222-228 are repeated for the following set of bits {d_(i+8);. . . ; d_(i+23)}.

Many additional embodiments are possible. For example, in the embodimentof FIG. 4, lookup table ZP′ is cancelled. In fact, the result ofsub-system ZP′ can be read from lookup table ZP because lookup tables ZPand ZP′ are identical as far as the bits Z[i] to Z[i+4] are concerned.In a similar way, lookup table R_(e)′ in the embodiment of FIG. 4 iscancelled and the values of bits R′_(e)[i] to R′_(e)[i+4] are read fromlookup table R_(e) because lookup tables R_(e) and R_(e)′ are identical.This further reduces the memory space necessary to implement the turboencoding method.

Each sub-system r[i+5] or r′[i+5] can be split into two sub-systems, thevalues of the first sub-system depending only on the value of the set ofbits {d_(i−1); . . . ; d_(i+3)} or {ie_(i−1); . . . ; e_(i+3)}, and thevalues of the second sub-system depending only on the value of theremainder r[i] or r′[i].

The memory space necessary to implement the above channel encodingmethod can be further reduced by splitting at least one of thesub-systems into at least two sub-systems. For example, sub-system DP1can be split into two sub-systems DP11 and DP12, according to thefollowing relation:

DP1=DP11⊕DP12  (20)

where:

$\begin{matrix}{{{DP}\; 11} = \left\{ \begin{matrix}{{{DP}\; {11\lbrack i\rbrack}} = d_{i}} \\{{{DP}\; {11\left\lbrack {i + 1} \right\rbrack}} = {d_{i + 3} \oplus d_{i + 1} \oplus d_{i}}} \\{{{DP}\; {11\left\lbrack {i + 2} \right\rbrack}} = d_{i + 1}} \\{{{DP}\; {11\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 2} \oplus d_{i + 1}}} \\{{{DP}\; {11\left\lbrack {i + 4} \right\rbrack}} = d_{i + 2}} \\{{{DP}\; {11\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 3} \oplus d_{i + 2}}} \\{{{DP}\; {11\left\lbrack {i + 6} \right\rbrack}} = d_{i + 3}} \\{{{DP}\; {11\left\lbrack {i + 7} \right\rbrack}} = d_{i + 3}} \\{{{DP}\; {11\left\lbrack {i + 8} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 9} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 10} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 11} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 12} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 13} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 14} \right\rbrack}} = Ø} \\{{{DP}\; {11\left\lbrack {i + 15} \right\rbrack}} = Ø}\end{matrix} \right.} & (21) \\{{{DP}\; 12} = \left\{ \begin{matrix}{{{DP}\; {12\lbrack i\rbrack}} = {d_{i + 6} \oplus d_{i + 5} \oplus d_{i + 4}}} \\{{{DP}\; {12\left\lbrack {i + 1} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 5}}} \\{{{DP}\; {12\left\lbrack {i + 2} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 5}}} \\{{{DP}\; {12\left\lbrack {i + 3} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6} \oplus d_{i + 4}}} \\{{{DP}\; {12\left\lbrack {i + 4} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6}}} \\{{{DP}\; {12\left\lbrack {i + 5} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 5}}} \\{{{DP}\; {12\left\lbrack {i + 6} \right\rbrack}} = d_{i + 7}} \\{{{DP}\; {12\left\lbrack {i + 7} \right\rbrack}} = {d_{i + 6} \oplus d_{i + 4}}} \\{{{DP}\; {12\left\lbrack {i + 8} \right\rbrack}} = d_{i + 4}} \\{{{DP}\; {12\left\lbrack {i + 9} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 5} \oplus d_{i + 4}}} \\{{{DP}\; {12\left\lbrack {i + 10} \right\rbrack}} = d_{i + 5}} \\{{{DP}\; {12\left\lbrack {i + 11} \right\rbrack}} = {d_{i + 6} \oplus d_{i + 5}}} \\{{{DP}\; {12\left\lbrack {i + 12} \right\rbrack}} = d_{i + 6}} \\{{{DP}\; {12\left\lbrack {i + 13} \right\rbrack}} = {d_{i + 7} \oplus d_{i + 6}}} \\{{{DP}\; {12\left\lbrack {i + 14} \right\rbrack}} = d_{i + 7}} \\{{{{DP}\; {12\left\lbrack {i + 15} \right\rbrack}} = d_{i + 7}}\;}\end{matrix} \right.} & (22)\end{matrix}$

Symbol Ø means that no XOR operation should be executed between thecorresponding bits of DP11 and DP12 during the execution of XORoperations according to relation (20).

Sub-systems DP11 and DP12 can be pre-computed for each value of the setof bits {d_(i); . . . ; d_(i+3)} and {d_(i+4); . . . ; d_(i+7)},respectively and the results stored in lookup tables DP11 and DP12.Lookup tables DP11 and DP12 store 2⁴×8 and 2⁴×16 bits respectively.Thus, the total number of bits stored in lookup tables DP11 and DP12 issmaller than the number of bits stored in lookup table DP1.

What has been illustrated in the particular case of sub-system DP1 andlookup table DP1 can be applied to any of the sub-systems disclosedherein above such as sub-systems DP11. The smaller memory spacenecessary to implement one of the above encoding channel methods isachieved when each system has been split up into a succession ofsub-systems, the value of each of these sub-systems depending only onthe value of a set of two bits. However, in this situation, it isnecessary to carry out a large number of XOR operations between theresult of each sub-system to obtain the encoded bit stream. In fact, thenumber of operations to be executed by the processor proportionallyincreases with the number of lookup tables used.

At the end of turbo encoding, switches 36 and 66 are switched to connectthe outputs of XOR gates 28 and 58 to the second input of XOR gates 34and 64 respectively. This configuration of encoder 2 can be modeledusing a system of parallel XOR operations and utilized on microprocessor92. Preferably, the implementation of the end of the turbo encoding iscarried out using several smaller lookup tables than the onecorresponding to the whole modeled system using the teaching disclosedherein above.

The above teaching applies to any channel encoder corresponding to ahardware implementation having a shift register and XOR gates. It alsoapplies to any channel encoder used in other standards such as, forexample, the WMAN (Wireless Metropolitan Area Network) or otherstandards in wireless communications.

The channel encoding method has been described in the particular casewhere a block of 5 bits is inputted in the processor at each iterationof the method. The method can be generalized to other sizes of inputtedbit blocks, such as, to blocks having 8, 16 or 32 bits for example.

The above channel encoding method can be implemented in any type of userequipment as well as in a base station.

1. A channel encoding method of calculating, using a programmableprocessor, a code identical with a code obtained with a hardware channelencoder comprising, reading the result of a first sub-system of parallelXOR operations between shifted bits in a first pre-computed lookup tableat a memory address determined from the value of the inputted bits, thefirst pre-computed lookup table storing any possible result of the firstsub-system at respective memory addresses; and carrying out an XORoperation between the read result and the result of a second sub-systemof parallel XOR operations using the XOR instruction of the programmableprocessor.
 2. The method according to claim 1, wherein the methodfurther comprises reading the result of the second sub-system in asecond pre-computed lookup table at an address determined from the valueof the inputted bits, the second pre-computed lookup table recording anypossible result of the second sub-system at respective memory addresses.3. The method according to claim 2 to calculate a code identical with acode obtained with a hardware convolutional encoder, wherein the memoryaddresses used during the first and second reading steps are onlydetermined from the values of two successive sets of inputted bits. 4.The method according to claim 3 of calculating a code identical with acode obtained with a hardware channel encoder having at least a feedbackchain, the set of bits stored in the shift register being called aremainder, wherein the address used during one of the reading steps isonly determined from the current value of the remainder.
 5. The methodaccording to claim 1, the hardware channel encoder corresponding to asystem of XOR operations having N relations between P variables linkedto each other by XOR operations, each relation being designed to providethe value of one bit of the code, wherein each sub-system corresponds toa part of the system comprising a number of variables strictly smallerthan the number P.
 6. The method according to claim 1 of calculating acode identical with a code obtained with a hardware channel encoder, thechannel encoder comprising: at least two forward chains to output bits;and a multiplexer to carry out multiplexing operations of the output ofeach forward chain, wherein the result recorded in each of the lookuptables also utilizes the multiplexing operation.
 7. A memory comprisinginstructions to execute a channel encoding method according to claim 1,when the instructions are executed by a programmable processor.
 8. Amicroprocessor program comprising instructions to execute a channelencoding method according to claim 1, when the instructions are executedby a programmable processor.
 9. A channel encoder adapted to carry out achannel encoding method according to claim 1, the channel encodercomprising: a programmable processor adapted to execute an XOR operationin response to an XOR instruction; and a memory connected to theprocessor, wherein the memory comprises the first pre-computed lookuptable which stores the results of the first sub-system, and wherein theprocessor is adapted to read the result of the first sub-system in thefirst pre-computed lookup table, and to carry out an XOR operationbetween the read result and the result of the second sub-system of XORoperations using the XOR instruction of the programmable processor. 10.A channel encoder according to claim 9, wherein the memory comprises thesecond pre-computed lookup table which stores the results of the secondsub-system, and wherein the processor is adapted to read the result ofthe second sub-system in the second pre-computed lookup table.
 11. Userequipment, comprising a channel encoder according to claim
 9. 12. A basestation comprising a channel encoder according to claim 9.